류형록 | Engineering Portfolio · 전공 설계·실험

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VHDL 7개 블록 / GHDL 7/7 PASS

2026-07-30 / GHDL 6.0.0 / 11 VCD

회로·파형·계산

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2026-07-30 GHDL·CI 재검증

• Tool: GHDL 6.0.0 mcode
• Recovered source: Vivado 2023.2 project/XSim context 4건
• Original benches: assertion이 없어 PASS가 아닌 STIMULUS_COMPLETE 4/4
• Portable self-check: full adder, 4-bit adder, decoder, mux, 4-bit mux, Mealy 101, universal shift register 7/7 PASS
• Evidence: local log, machine-readable CSV, VCD 11개
• GitHub Actions: run 30494189374 PASS · controller-logic-verification artifact
• Verification summary
• Pull Request #1

자료: Vivado project/XSim context·GHDL 기능 시뮬레이션 / 합성·타이밍·보드 시험 자료: 미확보

Portable RTL Verification · Recovered Original / Portable Reconstruction / GHDL Rerun

Controller Logic progression

RTL 범위

RTL 7개 블록: 조합회로·FSM·범용 시프트 레지스터. Vendor-independent self-checking testbench와 원본·재구성별 디렉터리.

Architecture Progression

RTL flow